1. Field of the Invention
The present invention relates generally to an improved data processing system. More specifically, the present invention is directed to a computer implemented method, system, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases when executed in a batch computing environment.
2. Description of the Related Art
Today, computer systems have evolved into extremely sophisticated devices that may be found in many different settings. Typically, computer systems include a combination of hardware components, such as, for example, semiconductors, circuit boards, disk drives, peripheral devices, and the like, and software components, such as, for example, computer programs and applications. The combination of hardware and software components on a particular computer system defines the computing environment.
As advances in semiconductor processing and computer architecture continue to push rapidly the performance of computer hardware higher, more sophisticated computer software programs and applications have evolved to test diagnostically these sophisticated hardware designs. These tests are run on a group of processors known as a simulation farm. Such a farm could potentially comprise thousands of processors. The test cases are analyzed using the simulation farm, which is referred to as batch processing.
However, current testing programs run every available test case to verify hardware designs. Running every available test case to verify a hardware design has a high cost in terms of the amount of resources used. This high cost is especially true with regard to processor overhead.